The speed of a binary adder is limited, in part, by the speed at which any carry bit signal issued in the course of summing corresponding digits of the two binary numbers being added can be propagated through successive more significant digits of the adder. Prior art binary adders are disadvantageous in that the carry bit from a less significant digit within the adder cannot be propagated to the next more significant digit until a summation of the less significant digits has been completed.
Accordingly, it is the principal object of this invention to provide a binary adder having the capability of propagating any carry bit signal, calculated in the course of summing corresponding digits of the numbers being added, prior to the time the addition has been completed.
It is a further object of this invention to provide isolation between successive digits of the binary adder in order to prevent circuitry of more significant digits from affecting signals associated with less significant digits.
These objects are accomplished in accordance with the preferred embodiment of this invention by employing separate logic circuitry within each digit of the binary adder to determine the status of the output carry bit signal based solely on the status of bits from the corresponding digits of the numbers being added and the carry bit signal from the preceding less significant digit of the adder. The status of this output carry bit signal may be determined prior to the completion of the calculation of the sum of the corresponding digits of the numbers being added and the carry bit from the preceding less significant digit of the adder by means of this separate logic circuitry. Therefore, summation of more significant digits may be commenced by the binary adder prior to completion of the summation of less significant digits.
Interference with signals associated with less significant digits of the binary adder by circuitry associated with more significant digits is prevented by insertion of a logic inverter between the carry bit output of the less significant digit and the carry input of the succeeding more significant digit. This logic inverter causes the input carry signal for even digit positions to be complementary to the input signal for odd digit positions, and summing and carry circuitry within the even and odd digit positions of the adder is arranged accordingly.